Nivedita Shrivastava

Research Scholar (Full-time)
IIT Delhi, New Delhi, India
Contact: nivedita [dot] shrivastava at ee [dot] iitd [dot] ac [dot] in

Publications

  • SecOComp: A Fast and Secure Simultaneous Compression and Encryption Scheme, Nivedita Shrivastava and Smruti R. Sarangi, ArXiv, 2023 [pdf]
  • Securator: A Fast and Secure Neural Processing Unit, Nivedita Shrivastava and Smruti R. Sarangi High Performance Computer Architecture (HPCA), 2023 [pdf]
  • Towards an Optimal Countermeasure for Cache Side-Channel Attacks, Nivedita Shrivastava and Smruti Ranjan Sarangi, IEEE Embedded Systems Letters (ESL), 2022 [pdf]
  • PredStereo: An Accurate Real-time Stereo Vision System” Diksha Moolchandani, Nivedita Shrivastava, Anshul Kumar, and Smruti Ranjan Sarangi. Winter Conference on Applications of Computer Vision (WACV) 2022 [pdf]
  • A Survey of Hardware Architectures for Generative Adversarial Networks, Nivedita Shrivastava, Muhammad Abdullah Hanif, Sparsh Mittal, Smruti Ranjan Sarangi, and Muhammad Shafique, Journal of Systems Architecture (JSA) 118, 102227, 2022 [pdf]
  • Efficient Hardware Implementations of QTL cipher for RFID Applications, Nivedita Shrivastava, Pulkit Singh, and Bibhudendra Acharya, International Journal of High Performance Systems Architecture 9 (1), 1-10, 2020 [pdf]
  • Lightweight Hardware Architecture for Eight-Sided Fortress Cipher in FPGA, Nivedita Shrivastava and Bibhudendra Acharya, Advances in Data and Information Sciences: Proceedings of ICDIS, 179-190, 2019 [pdf]
  • A Novel Hardware Architecture for Rectangle Block Cipher, Nivedita Shrivastava, Pulkit Singh, and Bibhudendra Acharaya, Nanoelectronics, Circuits and Communication Systems: Proceeding of Nanoelectronics, Circuits and Communication Systems (NCCS) pp 169–181, 2018 [pdf]
  • VLSI Implementation of ESF and QTL Lightweight Ciphers, Nivedita Shrivastava, Bibhudendra Acharya, and Ajay Singh Raghuvanshi, Proceedings of the Fourth International Conference on Microelectronics, Computing and Communication Systems (MCCS) pp 513–525, 2020 [pdf]

Patents

  • System and Method for Improving Stereo Vision Accuracy, Diksha Moolchandani, Nivedita Shrivastava and Smruti Ranjan Sarangi. Filed at the Indian patent office. Date: June 24, 2021. Number: 202111028215

Talks

  • "Securator: A Fast and Secure Neural Processing Unit" (virtually at HPCA, March, 2023)
  • "Securator: A Fast and Secure Neural Processing Unit" at IIT Delhi, India (February, 2023)
  • "Secure Architectures for Neural Networks: Research Proposal" at (virtually) IIT Delhi, 2020
  • "Design of a Secure Electric Vehicle Charging System" at (virtually) Semiconductor Research Corporation, 2021
  • "RDTSC instruction and Cache-based Side Channel Attacks" (virtually) at Indo-Japan Research Meet, 2022
  • "A Novel Hardware Architecture for Rectangle Block Cipher" at Nanoelectronics, Circuits and Communication Systems, 2018
  • "Lightweight Hardware Architecture for Eight-Sided Fortress Cipher in FPGA" (virtually) at ICDIS, 2018

Research Interests

  • Hardware Accelerators for Neural Networks
  • Secure Design of Hardware Accelerators
  • Cache-based Side-channel Attacks
  • Information-theoritic Analysis of Side-channel Attacks