Design of a simultaneous compression and encryption scheme for neural networks

Language C++, Python, Verilog
Tool used Cadence genus tool, Vivado

Efficiently securing and compressing neural network models is a problem of significant interest due to its high popularity in various machine learning and computer vision applications. These models embody valuable intellectual property that must be protected. Traditional encryption ciphers can provide high security guarantees in order to secure the model, but their sizes are prohibitive for resource-constrained devices. In this work, we present a simultaneous compression and encryption approach for deep learning models, where the model weights are encrypted using chaotic maps. This work is submitted to Transactions of Circuits and Systems, 2023 and is under review.

Design of a secure neural network accelerator

Simulator Timeloop, in-house cycle accurate simulator
Tool used Cadence genus tool, ChaiDNN, Vivado

Securing deep neural networks is a problem of significant interest since an machine learning model incorporates high-quality intellectual property, features of data sets painstakingly collated by mechanical turks, and novel methods of training on large cluster computers. Sadly, attacks to extract model parameters are on the rise, and thus designers are being forced to create architectures for securing such models. We observe that it is possible to exploit the deterministic memory access patterns of DNNs even further, and maintain state information for only the current layer. This reduces the storage space, reduces the number of memory accesses, increases performance, and simplifies the design without sacrificing any security guarantees. This work is published in High-performance computer architectures (HPCA), 2023.

Study of countermeasures for cache-based side channel attacks

In the last 15 years, we have witnessed a never ending arm’s race between the attacker and the defender with respect to cache-based side-channel attacks. We have seen a slew of attacks, countermeasures (CMs), counterattacks, counter-countermeasures and so on. We analyze the evolution of this area, propose three necessary conditions for designing a successful CM, and then analyze timing and address-based CMs for popular algorithms such as AES and PRESENT. We show that an optimal yet trivial solution for timing-based CMs is possible. Furthermore, address-based CMs are inferior to timing-based CMs, and they can be broken in O(nlog(log(n))) time. This work is published in Embeddedd System Letters (ESL), 2022.

Study of hardware architectures for generative adversarial networks

As you might have noticed, the field of deep learning is growing very rapidly and these networks are getting computationally intensive with each passing second. Thus, custom hardware architectures are emerging to the rescue. We have written a survey paper on accelerating the genrative adversarial networks. The survey is quite exhaustive and covers all the kinds of optimizations to accelerate these networks. This work is published in Journal of Systems Architecture (JSA), 2022.

Design and implementation of optimized hardware architectures for lightweight ciphers

Language Verilog
Tool used Xilinx ISE Design suite

Various lightweight algorithms are proposed to solve security problem for various resource-constrained environments. In this work, optimised hardware implementations of lightweight block cipher QTL are proposed in order to provide security with optimum resource utilisation. In proposed reduced datapath architecture, resource utilisation is reduced and it gives good trade-off between area and performance. In proposed pipelined architecture, encryption round is divided into two sub-stages. This design methodology significantly improves the operating frequency. As a result, this design is apt for high-speed applications. Moreover, the proposed unified architecture combines three key scheduling designs into single design for QTL encryption and provides flexible security. All three architectures are extensively evaluated and compared on the basis of performance, area utilisation, energy requirement and power consumption for their implementations in different FPGA platforms. This work is published in High Performance System Architectures, 2020.

Color transferring and style rendering using neural network

Language Python, Matlab

In this work, we use a neural network to analyse the similarities between each element in a set of distinct colour and grayscale images. Using transfer learning, the colour was assigned to each group of grayscale pixels. VGG-16 was used for feature detection (encoder) and a simple decoder was used to colour the grayscale image. Using basic image processing techniques, transformed the final colour image into an oil painting (Gaussian filtering, gradient computation)

Design and exploration of a basic convolution engine in Vivado HLS

Language C++
Tool used Vivado

In this work, we designed a basic convolution engine in hardware and investigated the impact of introducing various optimization strategies on the architecture.

Extraction of retinal vessels and optic disk from fundus image using neural network

Language Python, Matlab

We trained a neural network architecture (U-Net) to automatically extract the disc and vessels from a fundus image.

Hardware implementation of circular CORDIC architecture

Language Verilog
Tool used Xilinx ISE Design suite

CORDIC uses shift-add operations for a variety of computational applications, including trigonometric and square-root calculations. We implement the architecture for CORDIC in hardware for both the rotation mode and vectoring mode design.